1. Field of the Invention
The invention relates generally to data processing. More particularly, the invention relates to the control of cross-triggering of diagnostic processes on a plurality of processing devices.
Multiprocessor systems are increasingly being used in such fields as mobile telecommunications, data networking, data storage and imaging. For example, a mobile phone handset may comprise multiple processor cores, a digital signal processing core (DSP) and one or more control processors. Accordingly, there is a requirement to provide an interconnection system for such multiprocessor systems to facilitate diagnostic cross-triggering of events between different processors during the product development stage. In particular, the ability to achieve synchronised stop/start and step of multiple cores in a single integrated circuit is an important requirement. For example, in a system comprising three distinct cores A, B and C, if core A reaches a breakpoint on a given instruction then cores B and C should also be stopped as soon as possible. Furthermore, it may be desirable to allow one or more processor cores to generate either a trigger or an interrupt in dependence upon occurrence of a diagnostic event in another part of the integrated circuit. The requirement for control mechanism for cross-triggering of processing devices is applicable not only to processor cores but also to devices such as co-processors, Field Programmable Gate Arrays (FPGAs), Programmable Logic Devices (PLDs), Digital Signal Processors (DSP) and intelligent peripherals.
2. Description of the Prior Art
One known system for synchronised debugging is the “Aspex” system developed by Allant Software of California, USA. In this system stop/start/step operations are closely co-ordinated between the processors and Aspex independently sets up each processor to perform the desired action, then a final execute sequence is sent to all of the processors. Cross-triggering of breakpoints is achieved using hardware signalling. FIG. 71 of the accompanying drawings schematically illustrates how four processor cores are connected to effect cross-triggering in the Allant system. In this system the cross-triggering matrix is implemented via a Complex Programmable Logic Device (CPLD) 5100 comprising two groups of enable latches with memory mapped enable switches. The registers allow the user to specify which processor can interrupt another. FIG. 72 of the accompanying drawings illustrates the structure of the CPLD 5100. It can be seen that the output of each processor is routed to each of the three other processors and the three possible inputs to each processor are supplied to an OR gate associated with that processor. For example output of a first enable gate 5200 for processor 2 is fed to a second set of enable gates 5300 corresponding to processors 1, 3 and 4, the outputs of which are fed to OR gates 5400, 5700 and 5600 corresponding to cores 1, 3 and 4 respectively. The Aspex system provides a direct core to core mapping via a series of latches. As such, the Aspex matrix mapping increases in complexity as the number of cores increases and has the disadvantage that it is not readily scalable.
Another known cross-triggering system is an emulation bus proprietary to Texas Instruments. According to this system a bus line is used as a communication channel for a plurality of possible signals. However, access to a communication channel on the bus is dependent upon the current signalling state of the system.